A single-phase direct buck-boost AC–AC converter with minimum number of components

In this paper, a single-phase direct pulse width modulation (PWM) buck-boost AC–AC converter is proposed. The proposed converter utilizes a minimum number of semiconductor switches and passive components that decreases the converter power losses and offers high efficiency. It can be operated with simple PWM control and doesn’t require soft-commutation strategies. It does not suffer from input source shoot-through and commutation problems. Moreover, it supplies both continuous input and output currents. The common sharing ground of the input and output gives the proposed converter the feature that it can be utilized for voltage sag and swell compensation. A comparison of the proposed converter performance with similar existing converters is presented. Also, detailed circuit analysis, component design guidelines, and simulation results using the MATLAB/Simulink environment are demonstrated. A laboratory prototype has been built and tested to validate the converter performance and confirm the results obtained by computer simulation.

Switching strategy. The gating signals are generated by a conventional carrier-based pulse-width modulation (PWM) method, as shown in Fig. 2. Where D is the duty cycle and T s is the switching time period.
The PWM signal goes to the gates of the switches S 1 and S 2 , while its complementary goes to the gates of S 3 and S 4 , as shown in Fig. 2. There are two modes of operation during each half cycle of the input voltage. There is only one switch ON, and the body diode of another switch is forward biased during each mode of operation. Therefore, it has a continuous current waveform that indicates high current quality. www.nature.com/scientificreports/

Modes of operation.
(I) During the positive half cycle of the input voltage: (a) Mode 1 [0-DT s ]: Switch S 1 is turned-on during the DT s interval, as shown in Fig. 3a, and the body diode of S 2 is forward biased. This formed a path for the capacitor C 1 to discharge its stored energy through the inductor L 1 . The energy is stored in the inductor L 1 from the input source and the capacitor C 1 . Applying KVL to the circuit shown in Fig. 3a in steady state operation, we get where v in represents the input voltage and the voltage drop across the input filter inductor L in is neglected.

(b) Mode 2 [DTs-Ts]:
During this mode of operation, the switch S 4 is turned-on, and the body diode of S 3 is forward biased for an interval (1-D)T s as shown in Fig. 3b. The energy stored in the inductor L 1 is delivered to  The operation principle of the proposed converter is the same as that in the positive half cycle. The inductor L 1 stored energy from the source and the capacitor C 1 through the path formed by the switch S 2 and the body diode of S 1 , as shown in Fig. 3c. The energy was then discharged into the load via the path formed by the switch S 3 and the body diode of S 4 , as shown in Fig. 3d.

Parameter's design of the proposed converter
The passive components are mainly designed by considering their maximum tolerable current and voltage ripples. The inductor current ripple and capacitor voltage ripple can be obtained from the following equations: The inductor maximum tolerable current ripple is taken as a factor α% from its maximum rms current I max l−rms .  www.nature.com/scientificreports/ Substituting by Eqs. (1), and (8) in Eq. (6), and for maximum inductor current I max l−rms = I o−rms 1−D the inductor equation will be as follows: The maximum allowable voltage ripple for the capacitor C 1 is taken as a factor that is defined β% of the peak voltages across it (�v c = βv c ) . Substituting by Eq. (4) in (7) for an interval (1-D)T s .
Considering an ideal circuit then, the capacitor C 1 can be obtained as where I o-rms is the rms value of the load current, P o is the output power, and f sw is the switching frequency.
For selecting the required ratings of the semiconductor switches of the proposed converter, the peak voltages and currents of the semiconductor switches are calculated from Eqs. (13) and (14).

Calculation of power losses and efficiency
Power losses calculation. Conduction losses, switching losses, and blocking losses are the three types of power losses in any semiconductor switch (IGBT or diode). The blocking losses are low compared to the other two parts and can be neglected 33 .
Conduction losses. The instantaneous conduction losses in the IGBT (P cond.IGBT ) are obtained by multiplying the ON state voltage of the switch and the current following through it.
where V CE0 is the zero-current collector-emitter voltage during on-state, R C is the collector-emitter resistance during on-state, and i(t) is the current following through the IGBT that equals the inductor current (i L1 ).
There is only one IGBT operating in each mode of operation, so the total conduction losses for the four IGBTs are equivalent to the conduction losses of a single IGBT if it is continuously operating during the full cycle. The average value of the conduction losses can be given by the integration over a half of the periodic time, as the positive and negative half cycles are similar. The IGBT current is the same as the inductor current (i L1 ), thus the average value of conduction losses can be given as: where I avg , I rms are the average and RMS values of the switch current. Similarly, the average conduction losses of the diode are given as: where V D0 is the diode zero-current voltage, R D is the diode on-state resistance.
The current path is formed by only one IGBT and the body diode of another one during each mode of operation. Therefore, the total conduction losses can be expressed as the sum of the conduction losses for one IGBT and one diode given by Eqs. (16) and (17), respectively.
Switching losses. The switching losses of the switch (P sw ) can be expressed as: www.nature.com/scientificreports/ where W on and W off are the energy dissipated during turn-on and turn-off times, respectively 34 . There are two switches that operate respectively during each half cycle, the average switching losses for the proposed converter equal to the sum of the switching losses for the two switches considering that they are turned on and off along the overall cycle.
Passive components power losses calculation. The power losses in the input inductor (L in ), the main inductor (L 1 ), and the main capacitor (C 1 ) can be calculated as: where R L.in , R L1 , and R C1 are the internal resistance of the input inductor (L in ), inductor (L 1 ), and the capacitor (C 1 ), respectively. The total power losses in the passive elements are expressed as: Converter efficiency. The converter output power can be expressed as: The converter power losses are the summation of the losses in the switches and passive component losses given by Eqs. (18), (20), and (24).
The converter input power can be expressed as: The percentage efficiency of the converter can be calculated from Eqs. (25) and (27) as: Calculation of input power factor. The input power factor (PF) can be obtained as:

Simulation results
The model of the proposed converter is developed and simulated in the MATLAB/Simulink environment. The circuit performance is evaluated at switching frequency f sw = 2 kHz with converter parameters summarized in Table 1. www.nature.com/scientificreports/ According to Eq. (5), the proposed converter offers a boost operation when D is greater than 0.5, and a buck operation when D is lower than 0.5. The suggested converter was designed and tested at a 2 kHz switching frequency with the parameters shown in Table 1 as it was designed with the available components in the laboratory.
Simulation results for Resistive load. The system is powered by a 50 V AC supply and is connected to a resistive load (R o = 50 Ω).
For boosting mode, the duty ratio is set to 0.65; the input voltage, output voltage, input current, and output current are shown in Fig. 4. It is illustrated that the output voltage equals 92.86 V at an input voltage of 50 V with a voltage gain of 1.857. Moreover, the voltage and current waveforms are continuous. The inductor current (i L1 ), capacitor voltage (v C1 ), and voltage stresses across S 1 and S 2 at D = 0.65 are shown in Fig. 5. The maximum voltage across the switches S 1 and S 2 nearly equals 200 V.
The Total Harmonic Distortion (THD) of the output voltage and the input current are demonstrated, respectively, as shown in Fig. 6. The value of THD for the output voltage is 4.87% and 2.1% for the input current, which are acceptable limits.
In bucking mode, the waveforms of the input and output voltages and currents at the duty ratio of 0.25 for an input voltage of 50 V are displayed in Fig. 7. The output voltage is equal to 16.67; thus, the voltage gain equals to 0.33. Figure 8 depicts the inductor current (i L1 ), capacitor voltage (v C1 ), and the voltages across S 1 and S 2 at D = 0.25, where the voltage stresses on S 1 and S 2 nearly equal 95 V.
It is indicated from Figs. 5 and 8 that the switches voltage's stress equals the addition of the input and output voltages, as indicated from Eq. (13).
The previous results for the proposed converter and Figs. 4, 5, 6, 7 and 8 indicate the high quality of the input and output voltage and current waveforms with high converter efficiency. They also indicate that the input and output currents are continuous and the THD is within acceptable limits.
Simulation results for Inductive load. The simulation results for the proposed converter when supplied by a 50 V AC supply and connected to an inductive load (R o = 50 Ω and L o = 100 mH) are shown in Figs. 9, 10 and 11. Figure 9 presents the input and output voltage and current waveforms for boosting mode at D = 0.65. It is obvious that the input and output currents are semi-continous and nearly pure sinsouidal waveforms with low THD. The THD for input and output currents equals 2.16% and 0.3%, respictively.
The output voltage for the inductive load case is the same as for the resistive load, and it has the same voltage gain about 1.857.
Also, Fig. 10 indicates that the inductor current (i L1 ), capacitor voltage (v C1 ), and the voltage stresses across S 1 and S 2 are nearly the same as with the resistive load.
The performance of the proposed converter with the inductive load is investigated in bucking mode and the simulation results are given in Fig. 11. The supply current is nearly in-phase with the supply voltage; therefore, the supply power factor is nearly unity.
The proposed converter is redesigned at a higher switching frequency (f sw = 60 kHz) with components listed in Table 2    www.nature.com/scientificreports/ performance with high efficiency, reaching more than 97%. Also, its size will be very small, and the required input filter inductor and output filter capacitor will be very small, as given in Table 2. Figure 12 shows the input and output voltage and current waveforms when the duty ratio is set to D = 0.65 and f sw = 60 kHz . The converter offers an output voltage with voltage gain of G = 1.86. The converter efficiency equals 97% and the input power factor (P.F.) equals 0.9997 at D = 0.65. Also, the THD of the output voltage and input current is very low as they equal 1.55% and 0.68%, respectively, as shown in Fig. 13. Figures 12 and 13 indicate the high quality of the input and output voltages and currents waveforms. They also indicate the continuity of the input and output current waveforms and a low THD with a minimum passive component size.

Comparison between various AC-AC converters
A comparison of the proposed buck-boost AC-AC converter with some of the recent direct AC-AC converters is given in Table 3. The comparison is given in terms of the number of switches, power diodes, passive components, and switches operating at high switching frequency in each mode of operation. Based on the comparison in Table 3, it is clear that the proposed converter is designed with a minimum number of switches, and a minimum number of passive components than the competitor. Reducing the power electronics components means reducing the size, the total power losses, and the total cost of the converter.

Experimental results
The proposed converter is investigated in the laboratory to verify the aimed circuit. An experimental setup is implemented with components listed in Table 4, as shown in Fig. 14. The control system used for generating the gating signals of the controlled switches is a DSP-based laboratory model. Then, a drive circuit is used to amplify the voltage of the IGBTs pulses taken from the dSPACE (DS-1104) platform and to isolate the control system from the power system. The drive circuit can operate with a maximum frequency limit of 2 kHz due to the DSP limitations, so the experimental results are obtained at f sw = 2 kHz based on the sampling rate of the control board. The electrical specifications of the prototype at f sw = 2 kHz are given in Table 1   For bucking mode, the voltage gain equals 0.309 at D = 0.25 and the input power factor equals 0.9656, as shown in Fig. 18. Figures 16 and 19 show the inductor current (i L1 ), capacitor voltage (v C1 ), and voltage stresses across S 1 and S 2 for boost and buck operation, respectively. As seen from these figures, the experimental results are in good agreement with the simulation results. In addition, the maximum value of the voltage across the switches is in good agreement with the calculated value from Eq. (13).   Fig. 22.
These figures indicate that the proposed converter operates with the inductive load with high quality nearly sinusoidal waveforms as well as it operates with the resistive load.
The efficiency of the proposed converter when operated with a 60 kHz switching frequency varies with the variation of the duty ratio for almost the same input voltage (50 V-rms) and the same load (R o = 50 Ω), as shown in Fig. 23. The proposed converter has a peak efficiency of 98.46% when the duty ratio is 0.25 and a minimum efficiency of 96.15% when the duty ratio is 0.75.
When the input voltage is 50 V, f sw is 2 kHz, and R o is 50 Ω, the efficiency of the proposed converter varies with the variation of the duty ratio, as shown in Fig. 23. Experimentally, the proposed converter offers a peak efficiency of 94.6% when the duty ratio is 0.25. The minimum efficiency of the proposed converter is 91.6% when the duty ratio is 0.75. Moreover, for the whole range of duty ratio variations, the efficiency of the proposed converter is more than 91.6% for almost the same input voltage and the same load, as shown in Fig. 23.
As noticed from Fig. 23, the efficiency of the proposed converter when operated with 60 kHz is higher than when operated with 2 kHz due to the large components used in the experimental setup in the laboratory that increase the power losses.
The proposed converter offers a higher efficiency than the converters described in 25 and 28 when operated at the same experimental conditions as the maximum efficiency achieved with the two converters are 95.2% and 96.8%, respectively. The high efficiency of the proposed converter is the result of the lower number of semiconductor switches and passive components utilized in the proposed converter.

Conclusion
This paper introduced a direct buck-boost AC-AC converter with a low count of semiconductor switches with a lower rating and a minimum number of passive components. Thus, the converter size and the power losses are decreased, and the converter efficiency increases. The switching algorithm is discussed and is very simple. The parameters' design procedures and circuit analysis were detailed. A comparative study with previous converters was carried out, indicating that the proposed converter is superior to other converters. The proposed topology has been verified via a simulation assessment and an experimental setup for different conditions. The THDs for the input and output waveforms are within acceptable limits. An excellent agreement is found between simulation and experimental results, achieving the suggested circuit. The circuit structure may be of special interest for voltage sag and swell compensation for improving the performance of power systems. www.nature.com/scientificreports/    www.nature.com/scientificreports/  www.nature.com/scientificreports/  www.nature.com/scientificreports/    www.nature.com/scientificreports/  www.nature.com/scientificreports/  www.nature.com/scientificreports/

Data availability
The datasets used and/or analyzed during the current study available from the corresponding author on reasonable request.  www.nature.com/scientificreports/